MC68030 Datasheet, PDF (30/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Introduction
The program counter (PC) contains the address of the next instruction to be executed by the
MC68030. During instruction execution and exception processing, the processor
automatically increments the contents of the PC or places a new value in the PC, as
appropriate.
31
16 15
31
16 15
0
A7' (ISP)
0
A7" (MSP)
INTERRUPT
STACK POINTER
MASTER STACK
POINTER
15
87
0
(CCR)
SR
STATUS REGISTER
31
0
VBR
VECTOR BASE
REGISTER
31
0
SFC
ALTERNATE FUNCTION
DFC
CODE REGISTERS
31
0
CACR
CACHE CONTROL
REGISTER
31
0
CAAR
CACHE ADDRESS
REGISTER
31
0
ACCESS
AC0
CONTROL
REGISTER 0
31
0
ACCESS
AC1
CONTROL
REGISTER 1
15
0
ACUSR
ACU STATUS
REGISTER
Figure 1-3. Supervisor Programming Model Supplement
The status register, SR, (see Figure 1-4) stores the processor status. It contains the
condition codes that reflect the results of a previous operation and can be used for
conditional instruction execution in a program. The condition codes are extend (X), negative
(N), zero (Z), overflow (V), and carry (C). The user byte containing the condition codes is the
only portion of the status register information available in the user privilege level, and it is
referenced as the CCR in user programs. In the supervisor privilege level, software can
access the full status register, including the interrupt priority mask (three bits) as well as
additional control bits. These bits indicate whether the processor is in:
1. One of two trace modes (T1, T0)
2. Supervisor or user privilege level (S)
3. Master or interrupt mode (M)
The vector base register (VBR) contains the base address of the exception vector table in
memory. The displacement of an exception vector is added to the value in this register to
access the vector table.
MOTOROLA
MC68030 USER’S MANUAL
1-7