MC68030 Datasheet, PDF (511/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
Table 12-2. Memory Access Time Equations at 20 MHz
(12-1) t_AVDL=(N-1)•t1–t2–t6–t47A
(12-2) t_SADL=(N-2)t•1–t9–t47A
(12-3) t_AVSL=(N-1)t•1–t6–t60
(12-4) t_SASL=(N-1)t•1–t3–t9–t60
(12-5) t_AVBHL=Nt•1;mst2–t6–t27A
(12-6) t_SABHL=(N-1)t•1–t9–t27A
(12-7) t_AVDV=Nt•1–t2–t6–t27
(12-8) t_SADV=(N-1)t•1–t9–t27
N=2
—
—
21 ns
1 ns
40 ns
20 ns
46 ns
26 ns
N=3
46 ns
26 ns
71 ns
51 ns
90 ns
70 ns
96 ns
76 ns
N=4
96 ns
76 ns
121 ns
101 ns
140 ns
120 ns
146 ns
126 ns
where:
tX
= Refers to AC Electrical Specification #X
t1
= The Clock Period
t2
= The Clock Low Time
t3
= The Clock High Time
t6
= The Clock High to Address Valid Time
t9
= he Clock Low to AS Low Delay
t27 = The Data-In to Clock Low Setup Time
t27A = The BERR/HALT to Clock Low Setup Time
t47A = The Asynchronous Input Setup Time
t60 = The Synchronous Input to CLK High Setup Time
N
= The Total Number of Clock Periods in the Bus Cycle (Nonburst)
(N≥2 for Synchronous Cycles; N≥3 for Asynchronous Cycles)
N=5
146 ns
126 ns
171 ns
151 ns
190 ns
170 ns
196 ns
176 ns
N=6
196 ns
176 ns
221 ns
201 ns
240 ns
220 ns
246 ns
226 ns
However, many local memory systems do not operate in a truly asynchronous manner
because the memory control logic can either be related to the MC68030's clock or worst
case propagation delays are known; thus, asynchronous setup times for the DSACKx
signals can be guaranteed. The timing requirements for this pseudo-synchronous DSACKx
generation is governed by the equation for t_AVDL.
Synchronous cycles use the STERM signal to terminate the current bus cycle. In bus cycles
of equal length, STERM has more relaxed timing requirements than DSACKx since an
additional 30 ns is available when comparing t_AVSL(or t_SASL) to t_AVDL (or t_SADL). The only
additional restriction is that STERM must meet the setup and hold times as defined by
specifications #60 and #61, respectively, for all rising edges of the clock during a bus cycle.
The value for tSASL when the total number of clock periods (N) equals two in Table 12-2
requires further explanation. Because the calculated value of this access time (see Equation
12-4 of Table 12-2) is zero under certain conditions, hardware cannot always qualify STERM
with AS at all frequencies. However, such qualification is not a requirement for the
MC68030. STERM can be generated by the assertion of ECS, the falling edge of S0, or most
simply by the output(s) of an address decode or comparator logic. Note that other devices
in the system may require qualification of the access with AS since the MC68030 has the
capability to initiate bus cycles and then abort them before the assertion of AS.
MOTOROLA
MC68030 USER’S MANUAL
12-15