MC68030 Datasheet, PDF (440/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
The bus controller consists of the micro bus controller, the instruction fetch pending buffer,
and the write pending buffer. These three resources carry out all writes and reads that miss
in the on-chip caches.
11.2.5.1 INSTRUCTION FETCH PENDING BUFFER. The instruction prefetch mechanism
includes a single long-word instruction fetch pending buffer. Interlocks are provided to
prevent this buffer from being overwritten by an instruction prefetch request before a
previously requested prefetch is completed.
11.2.5.2 WRITE PENDING BUFFER. The MC68030 incorporates a single write pending
buffer, allowing the microsequencer to continue execution after the request for a write cycle
proceeds to the bus controller. Interlocks prevent the microsequencer from overwriting this
buffer.
11.2.5.3 MICRO BUS CONTROLLER. The micro bus controller performs the bus cycles
issued to the bus controller by the rest of the processor. It implements any dynamic bus
sizing required and also controls burst operations.
When prefetching instructions from external memory, the micro bus controller utilizes long-
word read cycles. The processor reads two words, which may load two instructions at once
or two words of a multi-word instruction into the cache holding register (and the instruction
cache if it is enabled and not frozen). A special case occurs when prefetch, that corresponds
to an instruction word at an odd-word boundary, is not found in the cache holding register
(e.g., due to a branch to an odd-word location) with an instruction cache miss. From a 32-
bit memory, the MC68030 reads both the even and odd words associated with the long-word
base address in one bus cycle. From an 8- or 16-bit memory, the processor reads the even
word before the odd word. Both the even and odd word are loaded into the cache holding
register (and the instruction cache if it is enabled and not frozen).
MOTOROLA
MC68030 USER’S MANUAL
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