MC68030 Datasheet, PDF (259/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
8.1.1 Reset Exception
Assertion by external hardware of the RESET signal causes a reset exception. For details
on the requirements for the assertion of RESET, refer to 7.8 Reset Operation.
The reset exception has the highest priority of any exception; it provides for system
initialization and recovery from catastrophic failure. When reset is recognized, it aborts any
processing in progress, and that processing cannot be recovered. Figure 8-1 is a flowchart
of the reset exception, which performs the following operations:
1. Clears both trace bits in the status register to disable tracing.
2. Places the processor in the interrupt mode of the supervisor privilege level by setting
the supervisor bit and clearing the master bit in the status register.
3. Sets the processor interrupt priority mask to the highest priority level (level 7).
4. Initializes the vector base register to zero ($00000000).
5. Clears the enable, freeze, and burst enable bits for both on-chip caches and the write-
allocate bit for the data cache in the cache control register.
6. Invalidates all entries in the instruction and data caches.
7. Clears the enable bit in the translation control register and the enable bits in both trans-
parent translation registers of the MMU.
8. Generates a vector number to reference the reset exception vector (two long words)
at offset zero in the supervisor program address space.
9. Loads the first long word of the reset exception vector into the interrupt stack pointer.
10. Loads the second long word of the reset exception vector into the program counter.
After the initial instruction prefetches, program execution begins at the address in the
program counter. The reset exception does not flush the address translation cache (ATC),
nor does it save the value of either the program counter or the status register.
MOTOROLA
MC68030 USER’S MANUAL
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