MC68030 Datasheet, PDF (46/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Data Organization and Addressing Capabilities
A bit field operand is specified by:
1. A base address that selects one byte in memory,
2. A bit field offset that indicates the leftmost (base) bit of the bit field in relation to the
most significant bit of the base byte, and
3. A bit field width that determines how many bits to the right of the base bit are in the bit
field.
The most significant bit of the base byte is bit field offset 0, the least significant bit of the
base byte is bit field offset 7, and the least significant bit of the previous byte in memory is
bit offset –1. Bit field offsets may have values in the range of –2³¹ to 2³¹â€“1, and bit field
widths may range between 1 and 32 bits.
2.4 ADDRESSING MODES
The addressing mode of an instruction can specify the value of an operand (with an
immediate operand), a register that contains the operand (with the register direct addressing
mode), or how the effective address of an operand in memory is derived. An assembler
syntax has been defined for each addressing mode.
Figure 2–3 shows the general format of the single effective address instruction operation
word. The effective address field specifies the addressing mode for an operand that can use
one of the numerous defined modes. The (eaL designation is composed of two 3-bit fields:
the mode field and the register field. The value in the mode field selects one or a set of
addressing modes. The register field specifies a register for the mode or a submode for
modes that do not use registers.
15
14 13 12 11 10
9
8
7
6
5
0
X
X
X
X
X
X
X
X
X
X
EFFECTIVE ADDRESS
MODE
REGISTER
Figure 2-3. Single Effective Address
Many instructions imply the addressing mode for one of the operands. The formats of these
instructions include appropriate fields for operands that use only one addressing mode.
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