MC68030 Datasheet, PDF (410/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.4.13 Transfer Single Main Processor Register Primitive
The transfer single main processor register primitive transfers an operand between one of
the main processor's data or address registers and the coprocessor. This primitive applies
to general and conditional category instructions. Figure 10-33 shows the format of the
transfer single main processor register primitive.
15
14 13 12 11 10
9
8
7
6
5
4
3
2
0
CA
PC DR
0
1
1
0
0
0
0
0
0 D/A
REGISTER
Figure 10-33. Transfer Single Main Processor Register Primitive Format
This primitive uses the CA, PC, and DR bits as previously described. If the coprocessor
issues this primitive with CA=0 during a conditional category instruction, the main processor
initiates protocol violation exception processing.
Bit [3], the D/A bit, specifies whether the primitive transfers an address or data register. D/
A=0 indicates a data register, and D/A=1 indicates an address register. Bits [2-0] contain the
register number.
If DR=0, the main processor writes the long-word operand in the specified register to the
operand CIR. If DR=1, the main processor reads a long-word operand from the operand CIR
and transfers it to the specified data or address register.
10.4.14 Transfer Main Processor Control Register Primitive
The transfer main processor control register primitive transfers a long-word operand
between one of its control registers and the coprocessor. This primitive applies to general
and conditional category instructions. Figure 10-34 shows the format of the transfer main
processor control register primitive. This primitive uses the CA, PC, and DR bits as
previously described. If the coprocessor issues this primitive with CA=0 during a conditional
category instruction, the main processor initiates protocol violation exception processing.
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