MC68030 Datasheet, PDF (528/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
(UNABLE TO LOCATE ART)
Figure 12-17. Example MC68030 Hardware Configuration with
External Physical Cache
Normally, as soon as AS is asserted, circuit (C) immediately asserts the STERM signal to
terminate the bus cycle, assuming that the cache will produce a valid hit later in the cycle.
Circuit (C) also prevents the early termination from occurring from those cycles that access
operands that are noncachable or had missed in the cache on the previous cycle (and have
not already been retried). In this example, (C) prevents early termination of all CPU space
accesses, all write cycles (assuming a writethrough cache is implemented), cycles with
CIOUT asserted, and all cycles that missed in the cache on the previous cycle and were not
accesses to noncachable locations. The flip-flop in (C) latches the termination condition of
the current bus cycle at the rising edge of AS, and this status is used during the next cycle.
Other conditions to suppress early termination may be included as required by a particular
system, but propagation delays must be carefully considered in order that the output of (C)
be valid before the rising edge of state S1 (see Equation 12-3 of Table 12-2).
12-32
MC68030 USER’S MANUAL
MOTOROLA