MC68030 Datasheet, PDF (364/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.1.3 Coprocessor Instruction Format
The instruction set for a given coprocessor is defined by the design of that coprocessor.
When a coprocessor instruction is encountered in the main processor instruction stream, the
MC68030 hardware initiates communication with the coprocessor and coordinates any
interaction necessary to execute the instruction with the coprocessor. A programmer needs
to know only the instruction set and register set defined by the coprocessor in order to use
the functions provided by the coprocessor hardware.
The instruction set of an M68000 coprocessor uses a subset of the F-line operation words
in the M68000 instruction set. The operation word is the first word of any M68000 Family
instruction. The F-line operation word contains ones in bits 15-12 [15:12]=1111; refer to
Figure 10-1); the remaining bits are coprocessor and instruction dependent. The F-line
operation word may be followed by as many extension words as are required to provide
additional information necessary for the execution of the coprocessor instruction.
15
14
13
12
11
98
65
0
1
1
1
1
CpID
TYPE
TYPE DEPENDENT
Figure 10-1. F-Line Coprocessor Instruction Operation Word
As shown in Figure 10-1, bits 9-11 of the F-line operation word encode the coprocessor
identification code (CpID). The MC68030 uses the coprocessor identification field to indicate
the coprocessor to which the instruction applies. F-line operation words, in which the CpID
is zero, are not coprocessor instructions for the MC68030. If the CpID (bits 9-11) and the
type field (bits 6-8) contain zeros, the instruction accesses the on-chip memory
management unit of the MC68030. Instructions with a CpID of zero and a nonzero type field
are unimplemented instructions that cause the MC68030 to begin exception processing.
The MC68030 never generates coprocessor interface bus cycles with the CpID equal to
zero (except via the MOVES instruction).
CpID codes of 001-101 are reserved for current and future Motorola coprocessors and CpID
codes of 110-111 are reserved for user-defined coprocessors. The Motorola CpID code that
is currently defined is 001 for the MC68881 or MC68882 floating-point coprocessor. By
default, Motorola assemblers will use CpID code 001 when generating the instruction
operation codes for the MC68881 or MC68882 coprocessor instructions.
10-4
MC68030 USER’S MANUAL
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