MC68030 Datasheet, PDF (497/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.9 BUS ARBITRATION LATENCY
In a system that uses the MMU, the bus arbitration latency is affected by several factors.
The MC68030 does not relinquish the physical bus while it is performing a read-modify-write
operation. Since the address translation search is an extended read-modify-write operation,
the no-cache-case latency is incurred by the longest address translation search required by
the system.
Another bus arbitration delay occurs when a coprocessor or other device delays or fails to
assert DSACKx or STERM signals to terminate a bus cycle. The maximum delay in this case
is undefined; it depends on the length of the delay in asserting the signals.
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MC68030 USER’S MANUAL
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