MC68030 Datasheet, PDF (522/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
The fourth and last section of the memory bank is the address and data buffers. The address
buffers are shown as 74ALS244s, but 74AS244s and 74F244s are also acceptable. Two
inputs to the address buffers remain unused allowing the possibility for expansion up to 1
Mbyte without any additional devices when SRAMs of suitable density become available.
The RDCS signal, qualified with AS, controls the data buffers during read operations. The
address buffers are always enabled.
Some modifications to this design can improve performance. Specifically, circuitry to control
CBACK and thus prevent or discontinue a burst cycle is a simple addition. The circuitry
should have two functions: to prevent wraparound and to prevent bursting when a data
operand crosses a long-word boundary.
Not all systems require the performance of 20-MHz 2-1-1-1 burst cycles, nor will all systems
be able to afford the fast devices of this design. If the clock frequency is below approximately
17.5 MHz, the same support logic supports 2-1-1-1 burst cycles with 35-ns memory. If 20
MHz is still the frequency of choice, the designer may choose to run 3-1-1-1 burst cycles.
12.5.3 A 3-1-1-1 Burst Mode Memory Bank Using SRAMS
Figure 12-15 shows the complete 3-1-1-1 memory bank with 256K bytes that can operate
with a 20-MHz MC68030. The required parts include:
(32) 64K x 1 SRAMs 35-ns access time (Motorola's MCM6287-35 or equivalent)
(4) 74ALS244 buffers
(4) 74F374 latches
(2) 74F32 OR gates
(4) 74F191 counters
(1) PAL16L8D (or equivalent)
(2) inverters
(1) flip-flop
12-26
MC68030 USER’S MANUAL
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