MC68030 Datasheet, PDF (520/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
CLK
REFILL
STATUS
FIG 12-14
Figure 12-14. Example 2-1-1-1 Burst Mode Memory Bank at 20 MHz, 256K Bytes
The first section is completely contained within the PAL16L8D. The PAL equations are the
same as those provided in Figure 12-8 for the two-clock read, three-clock write memory
bank, although slightly modified to support the larger block of memory (use A18=A20
instead of A16=A18). The PAL generates six memory-mapped signals: four byte select
signals for write operations, a buffer control signal, and the cycle termination signal. The
byte select signals are only asserted during write operations when the processor is
addressing the 256K bytes contained in the memory bank, and then only when the
appropriate byte or bytes is being written to as indicated by the SIZ0, SIZ1, A0, and A1
signals. The four signals, UUCS, UMCS, LMCS, and LLCS, control data bits D24=D31,
D16=D23, D8=15, and D0=D7 respectively. AS is used to qualify the byte select signals to
avoid spurious writes to memory before the address is valid. During read operations, the
read chip select (RDCS) signal, qualified with AS, controls the data latches only (since the
memory is already enabled with its E input grounded). The last signal generated by the PAL
is the TERM signal. As the equation shows, TERM consists of two events: one for read
cycles and the other for write cycles. For read cycles, TERM is an address decode signal
that is asserted whenever the address corresponds to the encoded memory-mapped bank
of SRAM. Write operations use the DAS signal to qualify the address decode, which
lengthens write cycles to three clock periods. If a two-clock write cycle is required, this
design can be modified to incorporate the address and data latches used in Figure 12-12.
TERM is connected to the system's STERM and CBACK consolidation circuitry such that
both are asserted when TERM is asserted. The consolidation circuitry should have a
maximum propagation delay of 15 ns or less. If the system has no other synchronous
memory or ports, TERM can be connected directly to STERM, and CBACK may be
grounded.
The second section is the burst address generator which contains the four counters and the
inverter. The counters serve to both buffer the MC68030's address lines (A2 and A3) and to
provide the next long-word address during a burst operation. The 74F191s are
asynchronously preset at the beginning of every bus cycle when AS is negated. When AS
asserts, the counting is dependent on the CBREQ signal and the CLK signal. During writes,
CBREQ is always negated, and the counters serve only as address buffers. During reads,
if CBREQ asserts, the current value of counter bits Q1:Q0 are incremented on every falling
12-24
MC68030 USER’S MANUAL
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