MC68030 Datasheet, PDF (453/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
The following computations use the general Equation (11-2):
Execution Time
= CCea1+[CCop1-min(Hop1,Tea1)]+[CCea2-
min(Hea2,Top1)]+[CCop2-min(Hop2,Tea2)[+]CCea3-
min(Hea3,Top2)]+[CCop3-min(Hop3,Tea3)]+[CCea4-
min(Hea4,Top3)]+[CCop4-min(Hop4,Tea4)]
= 3+[2-min(0,1)]+[10-min(4,0)]+[3-min(0,0)]+[2-min(1,1)]+
[4 -min(2,0)]+[2-min(0,0)[+]12-min(0,0)]
= 3+2+10+3+1+4+2+12
= 37 clock periods
11.5 EFFECT OF WAIT STATES
The constraints of a system design may require the insertion of wait states in memory
cycles. When the bus or the memory device requires many wait states, instruction execution
time is increased. However, one or two wait states may have little effect on instruction
timing. Often the only effect of one or more wait states is to reduce bus idle time.
The effect of wait states on data accesses may be accounted for in the instruction-cache-
case timings.
To add the effect of wait states on data accesses:
1a. For nonmemory indirect effective address timings that include an operand read, add
the number of wait states (in clocks) to the tail and instruction-cache-case (CC)
times. The head is not affected.
1b. For memory indirect effective address timings that use the calculate <ea> tables and
have only one data read (for the address fetch), add the number of wait states to the
CC time only. The head and tail are not affected.
1c. For memory indirect effective address timings (fetch <ea>) that have two data reads
(for the address fetch), add the number of wait states for two reads to the CC time.
Add the number of wait states for one data read to the tail. The head is not affected.
11-18
MC68030 USER’S MANUAL
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