MC68030 Datasheet, PDF (303/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
If possible, when the ATC stores a new address translation, it replaces an entry that is no
longer valid. When all entries in the ATC are valid, the ATC selects a valid entry to be
replaced, using a pseudo least recently used algorithm. The ATC uses a validity bit and an
internal history bit to implement this replacement algorithm. ATC hit rates are application
dependent, but hit rates ranging from 98% to greater than 99% can be expected.
Each ATC entry consists of a logical address and information from a corresponding page
descriptor that contains the physical address. The 28-bit logical (or tag) portion of each entry
consists of three fields:
27
26 24
23
0
V
FC
LOGICAL ADDRESS
V — VALID
This bit indicates the validity of the entry. If V is set, this entry is valid. This bit is set
when the MC68030 loads an entry. A flush operation clears the bit. Specifically, any of
these operations clear the V bit of an entry:
• A PMOVE instruction with the FD bit equal to zero that loads a value into the CRP,
SRP, TC, TT0, or TT1 register.
• A PFLUSHA instruction.
• A PFLUSH instruction that selects this entry.
• A PLOAD instruction for a logical address and FC that matches the tag for this entry.
The instruction writes a new entry (with the V bit set) for the specified logical address.
• The selection of this entry for replacement by the replacement algorithm of the ATC.
FC — FUNCTION CODE
This 3-bit field contains the function code bits (FC0-FC2) corresponding to the logical ad-
dress in this entry.
LOGICAL ADDRESS
This 24-bit field contains the most significant logical address bits for this entry. All 24 bits
of this field are used in the comparison of this entry to an incoming logical address when
the page size is 256 bytes. For larger page sizes, the appropriate number of least signifi-
cant bits of this field are ignored.
MOTOROLA
MC68030 USER’S MANUAL
9-15