MC68030 Datasheet, PDF (209/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
The simultaneous assertion of BERR and HALT during a bus cycle normally indicates that
the cycle should be retried. However, during the second, third, or fourth cycle of a burst
operation, this signal combination indicates a bus error condition, which aborts the burst
operation. In addition, the processor remains in the halted state until HALT is negated. For
information about bus error processing, refer to 7.5.1 Bus Errors.
Figure 7-37 is a flowchart of the burst operation. The following timing diagrams show various
burst operations. Figure 7-38 shows burst operations for long-word requests with two wait
states inserted in the first access and one wait cycle inserted in the subsequent accesses.
Figure 7-39 shows a burst operation that fails to complete normally due to CBACK negating
prematurely. Figure 7-40 shows a burst operation that is deferred because the entire
operand does not correspond to the same cache line. Figure 7-41 shows a burst operation
aborted by CIIN. Because CBACK corresponds to the next cycle, three long words are
transferred even though CBACK is only asserted for two clock periods.
The burst operation sequence begins with states S0–S3, which are very similar to those
states for a synchronous read cycle except that CBREQ is asserted. S4-S9 perform the final
three reads for a complete burst operation.
State 0
The burst operation starts with S0. The processor drives ECS low, indicating the
beginning of an external cycle. When the cycle is the first cycle of a read operation, OCS
is driven low at the same time. During S0, the processor places a valid address on A0–
A31 and valid function codes on FC0–FC2. The function codes select the address space
for the cycle. The processor drives R/W high, indicating a read cycle, and drives DBEN
inactive to disable the data buffers. SIZ0–SIZ1 become valid, indicating the number of
operand bytes to be transferred. CIOUT also becomes valid, indicating the state of the
MMU CI bit in the address translation descriptor or in the appropriate TTx register.
State 1
One-half clock later in S1, the processor asserts AS to indicate that the address on the
address bus is valid. The processor also asserts DS during S1. CBREQ is also asserted,
indicating that the MC68030 can perform a burst operation into one of its caches and can
read in four long words. In addition, ECS (and OCS, if asserted) is negated during S1.
State 2
The selected device uses R/W, SIZ0–SIZ1, A0–A1, and CIOUT to place the data on the
data bus. (The first cycle must supply the long word at the corresponding long-word
boundary.) All of the byte sections (D24–D31, D16–D23, D8–D15, and D0–D7) of the data
bus must be driven since the burst operation latches 32 bits on every cycle. During S2,
the processor drives DBEN active to enable external data buffers. In systems that use
two-clock synchronous bus cycles, the timing of DBEN may prevent its use. At the
beginning of S2, the processor tests the level of STERM. If STERM is recognized, the
processor latches the incoming data at the end of S2. For the burst operation to proceed,
CBACK must be asserted when STERM is recognized. If the data for the current cycle is
MOTOROLA
MC68030 USER’S MANUAL
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