MC68030 Datasheet, PDF (256/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
(Refer to Section 10 Coprocessor Interface Description for a complete discussion of
coprocessor exceptions.) For all other exceptions, internal logic provides the vector number.
This vector number is used in the last step to calculate the address of the exception vector.
Throughout this section, 9 vector numbers are given in decimal notation.
For all exceptions other than reset, the third step is to save the current processor context.
The processor creates an exception stack frame on the active supervisor stack and fills it
with context information appropriate for the type of exception. Other information may also
be stacked, depending on which exception is being processed and the state of the processor
prior to the exception. If the exception is an interrupt and the M bit of the status register is
set, the processor clears the M bit in the status register and builds a second stack frame on
the interrupt stack.
The last step initiates execution of the exception handler. The processor multiplies the
vector number by four to determine the exception vector offset. It adds the offset to the value
stored in the vector base register to obtain the memory address of the exception vector.
Next, the processor loads the program counter (and the interrupt stack pointer (ISP) for the
reset exception) from the exception vector table in memory. After prefetching the first three
words to fill the instruction pipe, the processor resumes normal processing at the address in
the program counter. Table 8-1 contains a description of all the exception vector offsets
defined for the MC68030.
Table 8-1. Exception Vector Assignments (Sheet 1 of 2)
Vector
Number(s)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Vector Offset
Hex
Space
000
SP
004
SP
008
SD
00C
SD
010
SD
014
SD
018
SD
01C
SD
020
SD
024
SD
028
SD
02C
SD
030
SD
034
SD
038
SD
03C
SD
Assignment
Reset Initial Interrupt Stack Pointer
Reset Initial Program Counter
Bus Error
Address Error
Illegal Instruction
Zero Divide
CHK, CHK2 Instruction
cpTRAPcc, TRAPcc, TRAPV Instructions
Privilege Violation
Trace
Line 1010 Emulator
Line 1111 Emulator
(Unassigned, Reserved)
Coprocessor Protocol Violation
Format Error
Uninitialized Interrupt
STATUS
Asserted
—
—
YES
YES
NO
NO
NO
NO
NO
YES
NO
YES
—
NO
NO
YES
8-2
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