MC68030 Datasheet, PDF (504/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
The major concern of a system designer is to design a CS interface that meets the AC
electrical specifications for both the MC68030 (MPU) and the MC68881/MC68882 (FPCP)
without adding unnecessary wait states to FPCP accesses. The following maximum
specifications (relative to CLK low) meet these objectives:
t_CLK low to AS low≤(MPU Spec 1–MPU Spec 47A–FPCP Spec 19)
(1)
t_CLK low to CS low≤(MPU Spec 1–MPU Spec 47A–FPCP Spec 19)
(2)
Even though requirement (1) is not met under worst case conditions, if the MPU AS is
loaded within specifications and the AS input to the FPCP is unbuffered, the requirement is
met under typical conditions. Designing the CS generation circuit to meet requirement (2)
provides the highest probability that accesses to the FPCP occur without unnecessary wait
states. A PAL 16L8 (see Figure 12-3) with a maximum propagation delay of 10 ns,
programmed according to the equations in Figure 12-4, can be used to generate CS. For a
25-MHz system, ^tCLK low to CS low is less than or equal to 10 ns when this design is used.
Should worst case conditions cause t_CLK low to AS low to exceed requirement (1), one wait
state is inserted in the access to the FPCP; no other adverse effect occurs. Figure 12-5
shows the bus cycle timing for this interface. Refer to MC68881UM/AD, MC68881/MC68882
Floating-Point Coprocessor User's Manual, for FPCP specifications.
The circuit that generates CS must meet another requirement. When a nonfloating-point
access immediately follows a floating-point access, CS (for the floating-point access) must
be negated before AS and DS (for the subsequent access) are asserted. The PAL circuit
previously described also meets this requirement.
For example, if a system has only one coprocessor, the full decoding of the ten signals
(FC0–FC2 and A13–A19) provided by the PAL equations in Figure 12-4 is not absolutely
necessary. It may be sufficient to use only FC0–FC1 and A16–A17. FC0–FC1 indicate when
a bus cycle is operating in either CPU space ($7) or user-defined space ($3), and A16–A17
encode CPU space type as coprocessor space ($2). A13–A15 can be ignored in this case
because they encode the coprocessor identification code (CpID) used to differentiate
between multiple coprocessors in a system. Motorola assemblers always default to a CpID
of $1 for floating-point instructions; this can be controlled with assembler directives if a
different CpID is desired or if multiple coprocessors exist in the system.
MOTOROLA
MC68030 USER’S MANUAL
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