MC68030 Datasheet, PDF (332/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
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Figure 9-35. Root Pointer Register (CRP, SRP) Format
9.7.2 Translation Control Register
The translation control register (TC) is a 32-bit register that contains the control fields for
address translation. All unimplemented fields of this register are read as zeros and must
always be written as zeros.
Writing to this register optionally causes a flush of the entire ATC. When written with the E
bit (bit 31) set (translation enabled), a consistency check is performed on the values of PS,
IS, and TIx as follows. The TIx fields are added together until a zero field is reached, and
this sum is added to PS and IS. The total must be 32, or an MMU configuration exception
(refer to 9.7.5.3 MMU Configuration Exception) is taken. If an MMU configuration
exception occurs, the TC register is updated with the data, and the E bit is cleared. The
translation control register is shown in Figure 9-36.
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Figure 9-36. Translation Control Register (TC) Format
The fields of the TC register are:
Enable (E)
This bit enables and disables address translation:
0 — Translation disabled
1 — Translation enabled
A reset operation clears this bit. When translation is disabled, logical addresses are used
as physical addresses. The MMU instructions (PTEST, PLOAD, PMOVE, PFLUSH) can
be executed successfully, regardless of the state of the E bit. Additionally, even if the E
bit is set, the TC register can be updated with a value whose E bit is set. The state of the
E bit does not affect the use of the transparent translation registers.
Supervisor Root Pointer Enable (SRE)
This bit controls the use of the supervisor root pointer register (SRP):
0 — SRP disabled
1 — SRP enabled
When the SRP is disabled, both user and supervisor accesses use the translation table
defined by the CRP. When the SRP is enabled, user accesses use the CRP, and super-
visor accesses use the SRP.
9-44
MC68030 USER’S MANUAL
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