MC68030 Datasheet, PDF (399/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
A coprocessor can be designed to execute a cpGEN instruction concurrently with the
execution of main processor instructions and, also, buffer one write operation to either its
command or condition CIR. This type of coprocessor issues a null primitive with CA=1 when
it is concurrently executing a cpGEN instruction, and the main processor initiates another
general or conditional coprocessor instruction. This primitive indicates that the coprocessor
is busy and the main processor should read the response CIR again without reinitiating the
instruction. The IA bit of this null primitive usually should be set to minimize interrupt latency
while the main processor is waiting for the coprocessor to complete the general category
instruction.
Table 10-3 summarizes the encodings of the null primitive.
Table 10-3. Null Coprocessor Response Primitive Encodings
CA PC IA PF TF
General Instructions
Conditional Instructions
x
1 x x x Pass Program Counter to Instruction Same as General Category
Address CIR, Clear PC Bit, and Proceed
with Operation Specified by CA, IA, PF,
and TF Bits
1
0 0 x x Reread Response CIR, Do Not Service Same as General Category
Pending Interrupts
1
0 1 x x Service Pending Interrupts and Reread Same as General Category
the Response CIR
0
0 0 0 c If (Trace Pending) Reread Response CIR; Main Processor Completes Instruction
Else, Execute Next Instruction
Execution Based on TF=c.
0
0 1 0 c If (Trace Pending) Service Pending
Main Processor Completes Instruction
Interrupts and Reread Response CIR; Execution Based on TF=c.
Else, Execute Next Instruction
0
0 x 1 c Coprocessor Instruction Completed;
Main Processor Completes Instruction
Service Pending Exceptions or Execute Execution Based on TF=c.
Next Instruction
x = Don't Care
c = 1 or 0 Depending on Coprocessor Condition Evaluation
MOTOROLA
MC68030 USER’S MANUAL
10-39