MC68030 Datasheet, PDF (145/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

On-Chip Cache Memories
6.3.1.1 WRITE ALLOCATE. Bit 13, the WA bit, is set to select the write-allocation mode
(refer to 6.1.2.1 Write Allocation) for write cycles. Clearing this bit selects the no-write-
allocation mode. A reset operation clears this bit. The supervisor should set this bit when it
shares data with the user task or when any task maps multiple logical addresses to one
physical address. If the data cache is disabled or frozen, the WA bit is ignored.
6.3.1.2 DATA BURST ENABLE. Bit 12, the DBE bit, is set to enable burst filling of the data
cache. Operating systems and other software set this bit when burst filling of the data cache
is desired. A reset operation clears the DBE bit.
6.3.1.3 CLEAR DATA CACHE. Bit 11, the CD bit, is set to clear all entries in the data cache.
Operating systems and other software set this bit to clear data from the cache prior to a
context switch. The processor clears all valid bits in the data cache at the time a MOVEC
instruction loads a one into the CD bit of the CACR. The CD bit is always read as a zero.
6.3.1.4 CLEAR ENTRY IN DATA CACHE. Bit 10, the CED bit, is set to clear an entry in the
data cache. The index field of the CAAR (see Figure 6-15) corresponding to the index and
long-word select portion of an address specifies the entry to be cleared. The processor
clears only the specified long word by clearing the valid bit for the entry at the time a MOVEC
instruction loads a one into the CED bit of the CACR, regardless of the states of the ED and
FD bits. The CED bit is always read as a zero.
6-16
MC68030 USER’S MANUAL
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