MC68030 Datasheet, PDF (326/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
(UNABLE TO LOCATE ART)
Figure 9-32. Example Translation Tree Structure for Two Tasks
9.5.5.2 SUPERVISOR TRANSLATION TREE. A second protection mechanism uses a
supervisor translation tree. A supervisor translation tree protects supervisor programs and
data from access by user programs and user programs and data from access by supervisor
programs. Access is granted to the supervisor programs which can access any area of
memory with the move address space (MOVES) instruction. When the SRE bit in the TC
register is set, the translation tree pointed to by the SRP is selected for all supervisor level
accesses. This translation tree can be common to all tasks. This technique segments the
logical address space into user and supervisor areas without adding the function code level
to the translation trees.
9.5.5.3 SUPERVISOR ONLY. A third mechanism protects supervisor programs and data
without segmenting the logical address space into supervisor and user address spaces. The
long formats of table descriptors and page descriptors contain S bits to protect areas of
memory from access by user programs. When a table search for a user access encounters
an S bit set in any table or page descriptor, the table search is completed and an ATC
descriptor corresponding to the logical address is created with the B bit set. The subsequent
retry of the user access results in a bus error exception being taken. The S bit can be used
to protect the entire area of memory defined in a branch of the translation tree or only one
or more pages from user program access.
9.5.5.4 WRITE PROTECT. The MC68030 provides write protection independently of the
segmented address spaces for programs and data. All table and page descriptors contain
WP bits to protect areas of memory from write accesses of any kind. When a table search
encounters a WP bit set in any table or page descriptor, the table search is completed and
an ATC descriptor corresponding to the logical address is created with the WP bit set. The
subsequent retry of the write access results in a bus error exception being taken. The WP
bit can be used to protect the entire area of memory defined in a branch of the translation
tree, or only one or more pages from write accesses. Figure 9-33 shows a memory map of
the logical address space organized to use S and WP bits for protection. Figure 9-34 shows
an example translation tree for this technique.
9-38
MC68030 USER’S MANUAL
MOTOROLA