MC68030 Datasheet, PDF (166/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
Figures 7-15 and 7-16 show an example of a long-word transfer to an odd address in long-
word-organized memory. In this example, a long-word access is attempted beginning at the
least significant byte of a long-word-organized memory. Only one byte can be transferred in
the first bus cycle. The second bus cycle then consists of a three-byte access to a long-word
boundary. Since the memory is long-word organized, no further bus cycles are necessary.
Figure 7-17 shows the equivalent operation for a cachable data read cycle.
7.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment
The combination of operand size, operand alignment, and port size determines the number
of bus cycles required to perform a particular memory access. Table 7-6 shows the number
of bus cycles required for different operand sizes to different port sizes with all possible
alignment conditions for write cycles and noncachable read cycles.
Table 7-6. Memory Alignment and Port Size Influence on Write Bus Cycles
A1/A0
Instruction*
Byte Operand
Word Operand
Long-Word Operand
00
1:2:4
1:1:1
1:1:2
1:2:4
Number of Bus Cycles
01
10
N/A
N/A
1:1:1
1:1:1
1:2:2
1:1:2
2:3:4
2:2:4
Data Port Size — 32 Bits:16 Bits:8 Bits
*Instruction prefetches are always two words from a long-word boundary.
11
N/A
1:1:1
2:2:2
2:3:4
This table shows that bus cycle throughput is significantly affected by port size and
alignment. The MC68030 system designer and programmer should be aware of and
account for these effects, particularly in time-critical applications.
MOTOROLA
MC68030 USER’S MANUAL
7-19