MC68030 Datasheet, PDF (247/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
S0
S2
S4
CLK
A31-A0
FC2-FC0
SIZ1-SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31-D0
BR
BG
S0
S2
BGACK
CONTROLLER
DMA DEVICE
Figure 7-60. Bus Arbitration Operation Timing
CONTROLLER
7.7.2 Bus Grant
The processor asserts BG as soon as possible after receipt of BR. This is immediately
following internal synchronization except during a read-modify-write cycle or following an
internal decision to execute a bus cycle. During a read-modify-write cycle, the processor
does not assert BG until the entire operation has completed. RMC is asserted to indicate
7-101
MC68030 USER’S MANUAL
MOTOROLA