MC68030 Datasheet, PDF (227/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
Table 7-8. DSACK, BERR, and HALT Assertion Results
Case
No.
Control
Signal
1
DSACKx
BERR
HALT
2
DSACKx
BERR
HALT
3
DSACKx
BERR
HALT
4
DSACKx
BERR
HALT
5
DSACKx
BERR
HALT
6
DSACKx
BERR
HALT
Asserted on Rising
Edge of State
N
N+2
A
S
NA
NA
NA
X
A
S
NA
NA
A/S
S
NA/A
X
A
S
NA
NA
A
X
NA
A
NA
NA
NA/A
X
A
S
A/S
S
A
X
NA
A
NA
A
Result
Normal cycle terminate and continue.
Normal cycle terminate and halt. Continue when HALT
negated.
Terminate and take bus error exception, possibly
deferred.
Terminate and take bus error exception, possibly
deferred.
Terminate and retry when HALT negated.
Terminate and retry when HALT negated.
LEGEND:
N — The number of current even bus state (e.g., S2, S4, etc.)
A — Signal is asserted in this bus state
NA — Signal is not asserted in this state
X — Don't care
S — Signal was asserted in previous state and remains asserted in this state
Table 7-8 shows various combinations of control signal sequences and the resulting bus
cycle terminations. To ensure predictable operation, BERR and HALT should be negated
according to the specifications in MC68030EC/D, MC68030 Electrical Specifications.
DSACKx, BERR, and HALT may be negated after AS. If DSACKx or BERR remain asserted
into S2 of the next bus cycle, that cycle may be terminated prematurely.
The termination signal for a synchronous cycle is STERM. An analogous set of bus cycle
termination cases exists in relationship to STERM assertion. Note that STERM and
DSACKx must never both be asserted in the same cycle. STERM has setup time (#60) and
hold time (#61) requirements relative to each rising edge of the processor clock while AS is
asserted. Bus error and retry terminations during burst cycles operate as described in
6.1.3.2 Burst Mode Filling, 7.5.1 Bus Errors, and 7.5.2 Retry Operation.
MOTOROLA
MC68030 USER’S MANUAL
7-81