MC68030 Datasheet, PDF (64/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Data Organization and Addressing Capabilities
For both the MC68020 and the MC68030, the register indirect modes can be extended
further. Since displacements can be 32 bits wide, they can represent absolute addresses or
the results of expressions that contain absolute addresses. This allows the general register
indirect form to be (bd,Rn) or (bd,An,Rn) when the base register is not suppressed. Thus,
an absolute address can be directly indexed by one or two registers (refer to Figure 2–6).
SYNTAX (bd,An,Rn)
bd
An
Rn
Figure 2-6. Using Absolute Address with Indexes
Scaling provides an optional shifting of the value in an index register to the left by zero, one,
two, or three bits before using it in the effective address allocation (the actual value in the
index register remains unchanged). This is equivalent to multiplying the register by one, two,
four, or eight or direct subscripting into an array of elements of corresponding size using an
arithmetic value residing in any of the 16 general registers. Scaling does not add to the
effective address calculation time. However, when combined with the appropriate derived
modes, it produces additional capabilities. Arrayed structures can be addressed absolutely
and then subscripted, (bd,Rn*scale). Another variation that can be derived is (An,Rn*scale).
In the first case, the array address is the sum of the contents of a register and a
displacement, as shown in Figure 2–7. In the second example. An contains the address of
an array and Rn contains a subscript.
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MC68030 USER’S MANUAL
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