MC68030 Datasheet, PDF (550/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Index
B
BERR Signal 5-9, 6-11, 7-6, 7-27, 8-7, 8-22,
8-25
Best Case 11-7
BG Signal 5-9, 7-43, 7-95–7-96
BGACK Signal 5-9, 7-97
Binary-Coded Decimal Instruction Timing
Table 11-43
Binary-Coded Decimal Instructions 3-10
Bit
CA 10-35
CD 6-21
CED 6-21
CEI 6-22
CI 6-22
Clear Data Cache 6-21
Clear Entry in Data Cache 6-21
Clear Entry in Instruction Cache 6-22
Clear Instruction Cache 6-22
Data Burst Enable 6-21
DBE 6-21
DR 10-36
ED 6-22
EI 6-23
Enable Data Cache 6-22
Enable Instruction Cache 6-23
FD 6-22
FI 6-23
Freeze Data Cache 6-22
Freeze Instruction Cache 6-23
IBE 6-22
Instruction Burst Enable 6-22
PC 10-35
WA 6-21
Write Allocate 6-21
Bit Field
Instruction Timing Table 11-47
Instructions 3-9
Operations 3-31
Bit Manipulation
Instruction Timing Table 11-46
Instructions 3-8
BKPT Instruction 7-74, 8-12, 8-22
Block Diagram 1-2, 9-2
MMU 9-2
Processor Resource 11-3
BR Signal 5-8, 7-43, 7-60, 7-96
Branch on Coprocessor Condition Instruction
10-13
Breakpoint Acknowledge 8-10
Cycle 7-74
Exception Signaled, Timing 7-74
Timing 7-74
Flowchart 7-74
Breakpoint Instruction 7-74, 8-22
Exception 8-22
Buffer
Instruction Fetch Pending 11-5
Write Pending 11-5
Burst
Cycle 7-59, 12-17
Mode
Cache Filling 6-10
Static RAM 12-24
Operation 7-59
Flowchart 7-61
Bus
Address 5-4, 7-3, 7-30, 12-4
Arbitration 7-96
Bus Inactive, Timing 7-103
Control 7-100
Flowchart 7-97
Latency 11-62
State Diagram 7-100
Timing 7-97
Control Signals 7-3
Controller 11-4
Data 5-4, 7-5, 7-30, 12-9, 12-24
Error
Exception 8-7, 10-72
Late, STERM, Timing 7-83
Late, Third Access, Timing 7-86
Late, With DSACKx, Timing 7-83
Second Access, Timing 7-86
Signal 5-9, 6-11, 7-6, 7-27, 8-7, 8-22
Without DSACKx Timing 7-83
Errors 7-82
Exceptions 7-75
Fault Recovery 8-27
Operation
Asynchronous 7-27
Synchronous 7-28–7-29
Synchronization 7-95
Timing 7-96
Transfer Signals 7-1
Index-2
MC68030 USER’S MANUAL
MOTOROLA