MC68030 Datasheet, PDF (480/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.12 Shift/Rotate Instructions
The shift/rotate instruction table indicates the number of clock periods needed for the
processor to perform the specified operation on the given addressing mode. Footnotes
indicate when it is necessary to account for the appropriate effective address time. The
number of bits shifted does not affect the execution time, unless noted. For instruction-cache
case and for no-cache case, the total number of clock cycles is outside the parentheses. The
number of read, prefetch, and write cycles is given inside the parentheses as (r/p/w). The
read, prefetch, and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
LSd
%
LSd
+
LSd
*
LSd
ASL
ASL
*
ASL
ASR
% ASR
+
ASR
*
ASR
ROd
ROd
*
ROd
ROXd
*
ROXd
#〈data〉,Dy
Dx,Dy
Dx,Dy
Mem by 1
#〈data〉,Dy
Dx,Dy
Mem by 1
#〈data〉,Dy
Dx,Dy
Dx,Dy
Mem by 1
#〈data〉,Dy
Dx,Dy
Mem by 1
Dn
Mem by 1
4
0
6
0
8
0
0
0
2
0
4
0
0
0
4
0
6
0
10
0
0
0
4
0
6
0
0
0
10
0
0
0
d Direction of shift/rotate: L or R
* Add Fetch Effective Address Time
% Indicates shift count is less than or equal to the size of data
+ Indicates shift count is greater than size of data
I-Cache Case
4(0/0/0)
6(0/0/0)
8(0/0/0)
4(0/0/1)
6(0/0/0)
8(0/0/0)
6(0/0/1)
4(0/0/0)
6(0/0/0)
10(0/0/0)
4(0/0/1)
6(0/0/0)
8(0/0/0)
6(0/0/1)
12(0/0/0)
4(0/0/0)
No-Cache
Case
4(0/1/0)
6(0/1/0)
8(0/1/0)
4(0/1/1)
6(0/1/0)
8(0/1/0)
6(0/1/1)
4(0/1/0)
6(0/1/0)
10(0/1/0)
4(0/1/1)
6(0/1/0)
8(0/1/0)
6(0/1/1)
12(0/1/0)
4(0/1/0)
MOTOROLA
MC68030 USER’S MANUAL
11-45