MC68030 Datasheet, PDF (422/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.5.1.1 COPROCESSOR-DETECTED PROTOCOL VIOLATIONS. Protocol violation
exceptions are communication failures between the main processor and coprocessor
across the M68000 coprocessor interface. Coprocessor-detected protocol violations occur
when the main processor accesses entries in the coprocessor interface register set in an
unexpected sequence. The sequence of operations that the main processor performs for a
given coprocessor instruction or coprocessor response primitive has been described
previously in this section.
A coprocessor can detect protocol violations in various ways. According to the M68000
coprocessor interface protocol, the main processor always accesses the operation word,
operand, register select, instruction address, or operand address CIRs synchronously with
respect to the operation of the coprocessor. That is, the main processor accesses these five
registers in a certain sequence, and the coprocessor expects them to be accessed in that
sequence. As a minimum, all M68000 coprocessors should detect a protocol violation if the
main processor accesses any of these five registers when the coprocessor is expecting an
access to either the command or condition CIR. Likewise, if the coprocessor is expecting
an access to the command or condition CIR and the main processor accesses one of these
five registers, the coprocessor should detect and signal a protocol violation.
According to the M68000 coprocessor interface protocol, the main processor can perform a
read of either the save or response CIRs or a write of either the restore or control CIRs
asynchronously with respect to the operation of the coprocessor. That is, an access to one
of these registers without the coprocessor explicitly expecting that access at that point can
be a valid access. Although the coprocessor can anticipate certain accesses to the restore,
response, and control coprocessor interface registers, these registers can be accessed at
other times also.
The coprocessor cannot signal a protocol violation to the main processor during the
execution of cpSAVE or cpRESTORE instructions. If a coprocessor detects a protocol
violation during the cpSAVE or cpRESTORE instruction, it should signal the exception to the
main processor when the next coprocessor instruction is initiated.
The main philosophy of the coprocessor-detected protocol violation is that the coprocessor
should always acknowledge an access to one of its interface registers. If the coprocessor
determines that the access is not valid, it should assert DSACKx, to the main processor and
signal a protocol violation when the main processor next reads the response CIR. If the
coprocessor fails to assert DSACKx, the main processor waits for the assertion of that signal
(or some other bus termination signal) indefinitely. The protocol previously described
ensures that the coprocessor cannot halt the main processor.
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MC68030 USER’S MANUAL
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