MC68030 Datasheet, PDF (537/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
The instruction executed (IE) signal indicates the execution unit has just finished processing
an instruction. The IE signal asserts after STATUS negates from a one-clock cycle
assertion. The assertion of IE also generates a SAMPLE signal.
The external cycle start condition (ECSC) signal is used in conjunction with the AS signal to
determine if the address bus and data bus are valid in the current trace sample. Table 12-
6 lists the possible combinations of AS and ECSC and shows what parts of the traced
address and data bus are valid. The assertion of ECSC does not generate a SAMPLE
signal.
Table 12-6. AS and ECSC Indicates
AS
ECSC
Indicates
0
0
Both Address and Data Bus Are Valid
0
1
Both Address and Data Bus Are Valid
1
0
Address Bits (A0=A7) are Valid
Address Bits (A8=A31) Are Invalid
Data Bus Is Invalid
1
1
Both Address and Data Bus Are Invalid
Figure 12-24 shows the pin definitions for the PAL16R6 package used in the trace circuit.
These definitions are used by the PAL equations listed in Figure 12-25.
12.8 POWER AND GROUND CONSIDERATIONS
The MC68030 is fabricated in Motorola's advanced HCMOS process, contains
approximately 275,000 total transistor sites, and is capable of operating at clock frequencies
of up to 33.33 MHz. While the use of CMOS for a device containing such a large number of
transistors allows significantly reduced power consumption in comparison to an equivalent
NMOS circuit, the high clock speed makes the characteristics of power supplied to the
device very important. The power supply must be able to supply large amounts of
instantaneous current when the MC68030 performs certain operations, and it must remain
within the rated specification at all times. To meet these requirements, more detailed
attention must be given to the power supply connection to the MC68030 than is required for
NMOS devices that operate at slower clock rates.
12-41
MC68030 USER’S MANUAL
MOTOROLA