MC68030 Datasheet, PDF (445/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
1
23
4
5
6
7
8
9 10 11 12 13 14 15 16
CLOCK
BUS
ACTIVITY
READ
PREFETCH
PREFETCH
READ
PREFETCH
BUS
CONTROLLER
IDLE
READ FROM PREFETCH
IDLE
PREFETCH READ FROM PREFETCH
d16,An,Dn
n+8
n + 12
(d16,An)
n + 16
CALCULATE AND FETCH
SEQUENCER
SOURCE EA
IDLE
FOR MOVE
INSTRUCTION
EXECUTION TIME
MOVE.L (d16,An,Dn),Dn
CLOCK
COUNT
10
LEGEND:
1) MOVE.L (d16,An,Dn),Dn
2) #(data).W,(d16,An)
PERFORM
MOVE
CALCULATE AND FETCH
SOURCE EA
FOR CMPI
PERFORM
CMPI
CMPI.W #(data).W,(d16,An)
6
Figure 11-5. Processor Activity – Odd Alignment
Comparing the two alignments, the execution time of the MOVE instruction is eight clocks
for even alignment and 10 clocks for odd alignment, an average of nine clocks. Referring to
the table in 11.6.6 MOVE Instruction and the table in 11.6.1 Fetch Effective Address
(fea), the average no-cache-case time is 2+7 = 9 clocks. A similar calculation can be made
of the CMPI instruction, which has an average no-cache-case time of seven clocks.
The average no-cache-case timing rather than the maximum no-cache-case timing gives a
closer approximation of the actual timing of an instruction stream in many cases. The total
execution time of the two instructions in the previous example is 16 clocks for both even and
odd alignment. Adding the average no-cache-case timing of the given instructions also gives
16 clocks (9+7 = 16 clocks). It should be noted again that the no-cache-case time assumes
no overlap. Therefore, the actual execution time of an instruction stream may be less than
that given by adding the no-cache-case times. To factor in the effect of wait states for the
no-cache case, refer to 11.5 Effect of Wait States.
11.3.4 Actual Instruction-Cache-Case Execution Time Calculations
The overall execution time for an instruction may depend on the overlap with the previous
and following instructions. Therefore, to calculate instruction execution time estimations, the
entire code sequence to be evaluated must be analyzed as a whole. To derive the actual
instruction-cache-case execution times for an instruction sequence (under the assumptions
listed in 11.6 Instruction Timing Tables), the instruction-cache-case times listed in the
tables must be used, and the proper overlap must be subtracted for the entire sequence.
The formula for this calculation is:
where:
CC₁+[CC₂–min(H₂,T₁)]+[(CC₃–min(H₃,T₂)]+. . .
(11-1)
11-10
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