MC68030 Datasheet, PDF (535/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
The pipelined architecture of the MC68030 prefetches instructions and operands to keep the
three stages of the instruction pipe full. The pipeline allows concurrent operations to occur
for up to three words of a single instruction or for up to three consecutive instructions. While
sequential instruction execution is the norm, it is possible that prefetched data is not used
by the execution unit due to a nonsequential event. The STATUS signal allows trace
hardware to mark the progress of the execution unit as it processes program memory
operands and allows marking of some exceptions. Nonsequential events, where the entire
pipeline needs to reload before continuing execution, are marked by the REFILL signal.
External hardware typically has no visibility into on-chip cache memory operations.
However, the MC68030 provides a local address reference to increase visibility. Write
operations are totally visible since the MC68030 implements a writethrough policy allowing
external hardware to capture data. For read operations from on-chip cache memories, the
least significant byte of the address bus provides a local address reference.
The MC68030 begins an external cycle by driving the address bus and asserting the
external cycle start (ECS) signal. Address strobe (AS) asserts later in the cycle to validate
the address. If a hit occurs in the cache or the cache holding register, then the external cycle
is aborted and AS is not asserted. In addition, the low-order address bits (A0=A7) are not
involved in the address translation process performed by the on-chip MMU, creating a local
address reference which can be used by trace functions. All read cycles from the on-chip
cache memories cannot be captured externally since the cache access does not depend on
the availability of the external bus.
Figure 12-23 shows a trace interface circuit which can be used with a logic analyzer for
program debug. The nine input signals (DSACK1, DSACK0, CLK, AS, RESET, STATUS,
REFILL, STERM, and ECS) are connected to the MC68030 processor in the system under
development. Six output signals are generated to aid in capturing and analyzing data. In
addition to connecting the logic analyzer to the address bus, the data bus, and the bus
control signals, the trace interface signals (SAMPLE, PHALT, FILL, EP, IE, and ECSC)
should also be connected. The external clock probe of the logic analyzer connects to the
system CLK signal for synchronization. Setting up the logic analyzer for data capture
requires that samples be taken on the falling edge of the CLK signal when the SAMPLE
signal is high. Table 12-5 lists the parts required to implement this circuit.
12-39
MC68030 USER’S MANUAL
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