MC68030 Datasheet, PDF (524/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
The flip-flop connected to the TERM signal serves two purposes: first, the TERM signal is
delayed at the beginning of the cycle to insert the wait state for the first long word, and
second, the burst address generator is also prevented from incrementing the long word base
address until the first long-word has been latched by the 74F374s.
The performance enhancing modifications described for the 2-1-1-1 design also apply to this
design. Specifically, circuitry can be added to control CBACK and thus prevent or
discontinue a burst cycle. The circuitry should have two functions: first, to prevent
wraparound and second, to prevent bursting when a data operand crosses a long-word
boundary. Another enhancement might be to alter the TERM control circuitry with the
addition of a write latch mechanism to run two-clock writes.
The critical path for the 3-1-1-1 memory bank is not the first long-word access as in the 2-1-
1-1 memory bank, but rather the subsequent long words during burst cycles. No alternative
architecture can correct the critical path for the 2-1-1-1 burst cycle. However, for 3-1-1-1
burst cycles, the designer might consider memory banks which are 64 or 128 bits wide. In
this manner, the access time for the subsequent long words can be hidden underneath the
access of the previous long word(s).
12.6 EXTERNAL CACHES
To provide lower average access times to memory, some systems implement caches local
to the main processor that store recently used instructions and/or data. For the MC68030,
several architectural options are available to the cache designer. The primary decisions are
whether to configure the cache as an asynchronous or synchronous device and whether the
cache accesses are terminated early (before the cache lookup is complete) or only after
validation.
The MC68030 late BERR/HALT facility allows an external device to signal completion of a
bus cycle by asserting DSACKx or STERM and later (approximately one clock period or
one-half clock, respectively) aborting or retrying that cycle if an error condition is detected.
Since one critical access path in many memory structures is the assertion of DSACKx/
STERM to avoid additional wait states, the late abort capability allows the memory controller
to terminate a bus cycle before data is valid on the processor data bus. If the data validation
fails, the memory controller can then abort (BERR) or retry (BERR/HALT) the cycle. This
technique is useful in memory error detection schemes where the cycle can be terminated
as soon as data becomes available and the error checking can occur during the period
between the signaling of termination of the cycle and the latching of data by the processor
with a late retry or abort signaled upon error indication. Likewise, this technique can be used
in cache implementations in which the cache tag validation cannot be completed before
termination of the cycle must be signaled but the validation is completed before late abort or
retry must be indicated.
The major consideration in choosing whether or not to utilize late retry for an external cache
miss is the overhead involved in retrying a bus cycle after a miss in the cache. The minimum
penalty is the four clock periods required to retry the cycle (two clocks during which the miss
is detected and two clocks idle bus time), assuming that the bus control strobes (BERR and
HALT) are negated soon enough after the completion of the aborted cycle that the next cycle
can begin immediately. In evaluating this overhead, the projected cache miss rate
12-28
MC68030 USER’S MANUAL
MOTOROLA