MC68030 Datasheet, PDF (116/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Processing States
4.3 EXCEPTION PROCESSING
An exception is defined as a special condition that pre-empts normal processing. Both
internal and external conditions cause exceptions. External conditions that cause
exceptions are interrupts from external devices, bus errors, coprocessor detected errors,
and reset. Instructions, address errors, tracing, and breakpoints are internal conditions that
cause exceptions. The TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, RTE, and DIV
instructions can all generate exceptions as part of their normal execution. In addition, illegal
instructions, privilege violations, and coprocessor protocol violations cause exceptions.
Exception processing, which is the transition from the normal processing of a program to the
processing required for the exception condition, involves the exception vector table and an
exception stack frame. The following paragraphs describe the vector table and a
generalized exception stack frame. Exception processing is discussed in detail in Section
8 Exception Processing. Coprocessor detected exceptions are discussed in detail in
Section 10 Coprocessor Interface Description.
4.3.1 Exception Vectors
The vector base register (VBR) contains the base address of the 1024-byte exception vector
table, which consists of 256 exception vectors. Exception vectors contain the memory
addresses of routines that begin execution at the completion of exception processing. These
routines perform a series of operations appropriate for the corresponding exceptions.
Because the exception vectors contain memory addresses, each consists of one long word,
except for the reset vector. The reset vector consists of two long words: the address used
to initialize the interrupt stack pointer and the address used to initialize the program counter.
The address of an exception vector is derived from an 8-bit vector number and the VBR. The
vector numbers for some exceptions are obtained from an external device; others are
supplied automatically by the processor. The processor multiplies the vector number by four
to calculate the vector offset, which it adds to the VBR. The sum is the memory address of
the vector. All exception vectors are located in supervisor data space, except the reset
vector, which is located in supervisor program space. Only the initial reset vector is fixed in
the processor's memory map; once initialization is complete, there are no fixed
assignments. Since the VBR provides the base address of the vector table, the vector table
can be located anywhere in memory; it can even be dynamically relocated for each task that
is executed by an operating system. Details of exception processing are provided in Section
8 Exception Processing, and Table 8-1 lists the exception vector assignments.
4-6
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