MC68030 Datasheet, PDF (342/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
The PFLUSH instruction flushes (invalidates) address translation descriptors in the ATC.
PFLUSHA, a version of the PFLUSH instruction, flushes all entries. The PFLUSH instruction
flushes all entries with a specified function code or the entry with a specified function code
and logical address.
The PLOAD instruction performs a table search operation for a specified function code and
logical address and then loads the translation for the address into the ATC. The operating
system can use this instruction to initialize the ATC to minimize table searching during
program execution. Any existing entry in the ATC that translates the specified address is
flushed. The preload can be executed for either read or write attributes. If the write attribute
is selected (PLOADW), the MC68030 performs the table search and updates all history
information in the translation tables (used and modified bits) as if a write operation to that
address had occurred. Similarly, if the read attribute is selected (PLOADR), the history
information in the translation table (used bit) is updated as if a read operation had occurred.
The PLOAD instruction does not alter the MMUSR.
The PTEST instruction either searches the ATC or performs a table search operation for a
specified function code and logical address, and sets the appropriate bits in the MMUSR to
indicate conditions encountered during the search. The physical address of the last
descriptor fetched can be returned in an address register. The exception routines of the
operating system can use this instruction to identify MMU faults. The PTEST instruction
does not alter the ATC.
This instruction is primarily used in bus error handling routines. For example, if a bus error
has occurred, the handler can execute an instruction such as:
PTESTW #1,([A7, offset]),#7,A0
This instruction requests that the MC68030 search the translation tables for an address in
user data space (#1) and examine protection information. This particular logical address is
obtained from the exception stack frame ([A7, offset]). The MC68030 is instructed to search
to the bottom of the table (#7 — there cannot be more than six levels) and return the physical
address of the last table entry used in register A0. After executing this instruction, the
handler can examine the MMUSR for the source of the fault and use A0 to access the last
descriptor. Note that the PTESTR and PTESTW instructions have identical results except
for PTEST0 when either TTx register matches the logical address and the R/W bit of that
register is not masked.
The MMU instructions use the same opcodes and coprocessor identification (CpID) as the
corresponding instructions of the MC68851. All F-line instructions with CpID=0 (including
MC68851 instructions) that the MC68030 does not support automatically cause F-line
unimplemented instruction exceptions when their execution is attempted in the supervise
mode. If execution of a unimplemented F-line instruction with CpID=0 is attempted in the
user mode, the MC68030 takes a privilege violation exception. F-line instructions with a
CpID other than zero are executed as coprocessor instructions by the MC68030.
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MC68030 USER’S MANUAL
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