MC68030 Datasheet, PDF (396/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
Bit [13], the DR bit, is the direction bit. It applies to operand transfers between the main
processor and the coprocessor. If DR=0, the direction of transfer is from the main processor
to the coprocessor (main processor write). If DR=1, the direction of transfer is from the
coprocessor to the main processor (main processor read). If the operation indicated by a
given response primitive does not involve an explicit operand transfer, the value of this bit
depends on the particular primitive encoding.
10.4.3 Busy Primitive
The busy response primitive causes the main processor to reinitiate a coprocessor
instruction. This primitive applies to instructions in the general and conditional categories.
Figure 10-23 shows the format of the busy primitive.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 PC 1
0
0
1
0
0
0
0
0
0
0
0
0
0
Figure 10-23. Busy Primitive Format
This primitive uses the PC bit as previously described.
Coprocessors that can operate concurrently with the main processor but cannot buffer write
operations to their command or condition CIR use the busy primitive. A coprocessor may
execute a cpGEN instruction concurrently with an instruction in the main processor. If the
main processor attempts to initiate an instruction in the general or conditional instruction
category while the coprocessor is concurrently executing a cpGEN instruction, the
coprocessor can place the busy primitive in the response CIR. When the main processor
reads this primitive, it services pending interrupts (using a pre-instruction exception stack
frame, refer to Figure 10-41). The processor then restarts the general or conditional
coprocessor instruction that it had attempted to initiate earlier.
10-36
MC68030 USER’S MANUAL
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