MC68030 Datasheet, PDF (300/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
(UNABLE TO LOCATE ART)
Figure 9-8. Address Translation General Flowchart
If an access results in an ATC hit but the access is either a write or read-modify-write access
and the page is write protected, the memory cycle is also aborted, and a bus error exception
is taken. For a write or read-modify-write access, when the modified bit of the ATC entry is
not set, the memory cycle is aborted, a table search proceeds to set the modified bit in both
the page descriptor in memory and in the ATC, and the access is retried. If the modified bit
of the ATC entry is set and the bus error bit is not, assuming that neither TTx register
matches and the access is not to CPU space, the ATC provides the address translation to
the bus controller under two conditions: 1) if a read access does not hit in either on-chip
cache and 2) if a write or read-modify-write access is not write protected.
The preceding description of the general flowchart specifies several conditions that cause
the memory cycle to be aborted. In these cases, the bus cycle is aborted before the
assertion of AS.
9.2.2 Effect of RESET On MMU
When the MC68030 is reset by the assertion of the RESET signal, the E bits of the TC and
TTx registers are cleared, disabling address translation. This causes logical addresses to
be passed through as physical addresses to the bus controller, allowing an operating system
to set up the translation tables and MMU registers, as required. After it has initialized the
translation tables and registers, the E bit of the TC register can be set, enabling address
translation. A reset of the processor does not invalidate any entries in the ATC. An MMU
instruction (such as PMOVE) that flushes the ATC must be executed to flush all existing
valid entries from the ATC after a reset operation and before translation is enabled.
9.2.3 Effect of MMUDIS On Address Translation
The assertion of MMUDIS prevents the MMU from performing searches of the ATC and the
execution unit from performing table searches. With address translation disabled, logical
addresses are used as physical addresses. When an initial access to a long-word-aligned
data operand that is larger than the addressed port size is performed, the successive bus
cycles for additional portions of the operand always use the same higher order address bits
that were used for the initial bus cycle (changing A0 and A1 appropriately). Thus, if MMUDIS
is asserted during this type of operation, the disabling of address translation does not
become effective until the entire transfer is complete. Note that the assertion of MMUDIS
does not affect the operation of the transparent translation registers.
9-12
MC68030 USER’S MANUAL
MOTOROLA