MC68030 Datasheet, PDF (479/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.11 Single Operand Instructions
The single operand instruction table indicates the number of clock periods needed for the
processor to perform the specified operation on the given addressing mode. Footnotes
indicate when it is necessary to account for the appropriate effective address time. For
instruction-cache case and for no-cache case, the total number of clock cycles is outside the
parentheses. The number of read, prefetch, and write cycles is given inside the parentheses
as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
CLR
** CLR
NEG
*
NEG
NEGX
*
NEGX
NOT
*
NOT
EXT
NBCD
Scc
** Scc
TAS
** TAS
TST
*
TST
Dn
Mem
Dn
Mem
Dn
Mem
Dn
Mem
Dn
Dn
Dn
Mem
Dn
Mem
Dn
Mem
* Add Fetch Effective Address Time
**Add Calculate Effective Address Time
Head
Tail
2
0
0
1
2
0
0
1
2
0
0
1
2
0
0
1
4
0
0
0
4
0
0
1
4
0
3
0
0
0
0
0
I-Cache Case
2(0/0/0)
3(0/0/1)
2(0/0/0)
3(0/0/1)
2(0/0/0)
3(0/0/1)
2(0/0/0)
3(0/0/1)
4(0/0/0)
6(0/0/0)
4(0/0/0)
5(0/0/1)
4(0/0/0)
12(1/0/1)
2(0/0/0)
2(0/0/0)
No-Cache
Case
2(0/1/0)
4(0/1/1)
2(0/1/0)
4(0/1/1)
2(0/1/0)
4(0/1/1)
2(0/1/0)
4(0/1/1)
4(0/1/0)
6(0/1/0)
4(0/1/0)
5(0/1/1)
4(0/1/0)
12(1/1/1)
2(0/1/0)
2(0/1/0)
11-44
MC68030 USER’S MANUAL
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