MC68030 Datasheet, PDF (90/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Set Summary
3.2.9 System Control Instructions
Privileged instructions, trapping instructions, and instructions that use or modify the
condition code register (CCR) provide system control operations. Table 3–9 summarizes
these instructions. The TRAPcc instruction uses the same conditional tests as the
corresponding program control instructions. All of these instructions cause the processor to
flush the instruction pipe.
Instruction
ANDI
EORI
MOVE
MOVE
MOVEC
MOVES
ORI
RESET
RTE
STOP
BKPT
CHK
CHK2
ILLEGAL
TRAP
TRAPcc
TRAPV
ANDI
EORI
MOVE
ORI
Table 3-9. System Control Operations
Operand Syntax
#〈data〉,SR
#〈data〉,SR
〈ea〉,SR
SR,〈ea〉
USP,An
An,USP
Rc,Rn
Rn,Rc
Rn, 〈ea〉
〈ea〉,Rn
#〈data〉,SR
none
none
#〈data〉
#〈data〉
〈ea〉,Dn
〈ea〉,Rn
none
#〈data〉
none
#〈data〉
none
#〈data〉,CCR
#〈data〉,CCR
〈ea〉,CCR
CCR,〈ea〉
#〈data〉,CCR
Operand Size
Operation
Privileged
16
immediate data Λ SR → SR
16
immediate data x SR → SR
16
source → SR
16
SR → destination
32
USP → An
32
An → USP
32
Rc → Rn
32
Rn → Rc
8, 16, 32
Rn → destination using DFC
source using SFC → Rn
16
immediate data V SR → SR
none
assert RESET line
none
(SP) → SR; SP + 2 → SP; (SP) → PC; SP + 4 → SP;
Restore stack according to format
16
immediate data → SR; STOP
Trap Generating
none
run breakpoint cycle, then trap as illegal instruction
16, 32
if Dn < 0 or Dn > (ea), then CHK exception
8, 16, 32
if Rn < -lower bound or Rn > -upper bound, then CHK
exception
none
SSP — 2 → SSP; Vector Offset→ (SSP);
SSP — 4 → SSP; PC→ (SSP);
SSP — 2 → SSP; SR→ (SSP);
Illegal Instruction Vector Address → PC
none
SSP — 2 → SSP; Format and Vector Offset→(SSP)
SSP — 4 → SSP; PC→(SSP); SSP — 2 → SSP;
SR→(SSP); Vector Address → PC
none
16, 32
if cc true, then TRAP exception
none
if V, then take overflow TRAP exception
Condition Code Register
8
immediate data Λ CCR → CCR
8
immediate data ⊕ CCR → CCR
16
source → CCR
16
CCR → destination
8
immediate data V CCR → CCR
3-12
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