MC68030 Datasheet, PDF (514/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
20-MHz
OSCILLATOR
CONTROLLER
CLOCK (40 MHz)
3
BUS CLOCKS
(40 MHz)
MC68EC030
(40 MHz)
FIG 12-9
Figure 12-9. Example Two-Clock Read, Three-Clock Write Memory Bank
The first section consists of two 74F32 OR gates, a 74F74 D-type flip-flop, and a PAL16L8D.
Example PAL equations are provided in Figure 12-10. The PAL generates six memory-
mapped signals; four byte select signals for write operations, a buffer control signal, and the
cycle termination signal. The byte select signals are only asserted during write operations
when the processor is addressing the 64K bytes contained in the memory bank, and then
only when the appropriate byte (or bytes) is being written to as indicated by the SIZ0, SIZ1,
A0, and A1 signals. The four signals, UUCS, UMCS, LMCS, and LLCS, control data bits
D24=D31, D16=D23, D8=D15, and D0=D7, respectively. AS is used to qualify the byte
select signals to avoid spurious writes to memory before the address is valid. During read
operations, the read chip select (RDCS) signal, qualified with AS, controls the data buffers
only (since the memory is already enabled with its E input grounded). The last signal
generated by the PAL is the TERM signal. As its equation shows, TERM consists of two
events: one for read cycles and the other for write cycles. For read cycles, TERM is an
address decode signal that is asserted whenever the address corresponds to the encoded
memory-mapped bank of SRAM. For write operations, a delayed form of AS (DAS) is used
to qualify the same address decode, which lengthens write operations to three clock cycles.
The DAS signal generation is delayed from the clock edge by running the clock signal
through two 74F32 OR gates before connecting to the 74F74 D-type flip-flop. This
guarantees that the maximum propagation delay to generate the TERM signal does not
violate the synchronous input hold time of the MC68030. By increasing write operation to
three clock cycles, the MC68030 can easily meet the specified data setup time to the
SRAMs before the negation of the write strobes (W). TERM is then connected to the
system's STERM consolidation circuity. The consolidation circuitry should have no more
than 15 ns of propagation delay. If the system has no other synchronous memory or ports,
TERM may be connected directly to STERM.
12-18
MC68030 USER’S MANUAL
MOTOROLA