MC68030 Datasheet, PDF (512/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
Another way to optimize the CPU to memory access times in a system is to use a clock
frequency less than the rated maximum of the specific MC68030 device. Table 12-3
provides calculated t_AVDV (see Equation 12-7 of Table 12-2) results for an MC68030RC16
and MC68030RC20 operating at various clock frequencies. If the system uses other clock
frequencies, the above equations can be used to calculate the exact access times.
Table 12-3. Calculated t_AVDV Values for Operation at Frequencies
Less Than or Equal to the CPU Maximum Frequency Rating
Equation 12-7 ^tAVDV
Clocks Per BusCycle (N) and
Type
Wait
States
2 Clock Synchronous
0
3 Clock Synchronous
1
3 Clock Asynchronous
0
4 Clock Synchronous
2
4 Clock Asynchronous
1
5 Clock Synchronous
3
5 Clock Asynchronous
2
6 Clock Synchronous
4
6 Clock Asynchronous
3
MC68030RC20
Clock at Clock at
16.67 MHz 20 MHz
61
46
121
96
121
96
181
146
181
146
241
196
241
196
301
246
301
246
MC68030RC25
Clock at Clock at Clock at
16.67 MHz 20 MHz 25 MHz
68
53
38
—
128
103
78
128
103
78
188
153
118
188
153
118
248
203
158
248
203
158
308
253
198
308
253
198
12.4.2 Burst Mode Cycles
The memory access times for burst mode bus cycles follow the above equations for the first
access only. For the subsequent (second, third, and fourth) accesses, the memory access
time calculations depend on the architecture of the burst mode memory system.
Architectural tradeoffs include the width of the burst memory and the type of memory used.
If the memory is 128 bits wide, the subsequent operand accesses do not affect the critical
timing paths. For example, if a 3-1-1-1 burst accesses 128-bit-wide memory, the first access
is governed by the equations in Table 12-2 for N equal to three. The subsequent accesses
also use these values as a base but have additional clock periods added in. The second
access has one additional clock period, the third access has two additional clock periods,
and the fourth has three additional clock periods. Thus, the access time for the first cycle
determines the critical timing paths.
12-16
MC68030 USER’S MANUAL
MOTOROLA