MC68030 Datasheet, PDF (57/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Data Organization and Addressing Capabilities
2.4.15 Program Counter Memory Indirect Preindexed Mode
This mode is similar to the memory indirect preindexed mode described in 2.4.10 Memory
Indirect Preindexed Mode, but the PC is used as the base register. Both the operand and
operand address are in memory. The processor calculates an intermediate indirect memory
address by adding the PC contents, a base displacement (bd), and the scaled contents of
an index register. The processor accesses a long word at that address and adds the optional
outer displacement (od) to yield the effective address. The value of the PC is the address of
the first extension word. The reference is a program space reference and is only allowed for
reads (refer to 4.2 Address Space Types).
In the syntax for this mode, brackets enclose the values used to calculate the intermediate
memory address. All four user-specified values are optional. However, the user must supply
the assembler notation ZPC (zero value is taken for the PC) to indicate that the PC is not
used. This allows the user to access the program space without using the PC in calculating
the effective address. Both the base and outer displacements may be null, word, or long
word. When a displacement is omitted or an element is suppressed, its value is taken as
zero in the effective address calculation.
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER FIELD:
PROGRAM COUNTER:
EA = (bd + PC + Xn . SIZE * SCALE) + od
([bd, PC, Xn. SIZE*SCALE],od)
111
011
31
0
ADDRESS OF EXTENSION WORD
31
0
BASE DISPLACEMENT:
SIGN-EXTENDED VALUE
+
31
0
INDEX REGISTER
SIGN-EXTENDED VALUE
7
0
SCALE VALUE
X
+
31
0
INDIRECT MEMORY ADDRESS
POINTS TO
31
0
VALUE AT INDIRECT MEMORY
ADDRESS IN PROGRAM SPACE
31
0
OUTER DISPLACEMENT:
SIGN-EXTENDED VALUE
+
31
0
EFFECTIVE ADDRESS:
NUMBER OF EXTENSION WORDS:
1, 2, 3, 4 OR 5
OPERAND
MOTOROLA
MC68030 USER’S MANUAL
2-19