MC68030 Datasheet, PDF (274/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
CLK
IPEND
STATUS
STAT0
STAT1
PROCEED TO INTERRUPT
EXCEPTION PROCESSING
EXAMPLE 1: INTERRUPT EXCEPTION SIGNALED DURING STAT1
CLK
IPEND
STATUS
STAT1
PROCEED TO INTERRUPT
EXCEPTION PROCESSING
EXAMPLE 2: INTERRUPT EXCEPTION SIGNALED DURING STAT0
Figure 8-6. Examples of Interrupt Recognition and Instruction Boundaries
When processing an interrupt exception, the processor first makes an internal copy of the
status register, sets the privilege level to supervisor, suppresses tracing, and sets the
processor interrupt mask level to the level of the interrupt being serviced. The processor
attempts to obtain a vector number from the interrupting device using an interrupt
acknowledge bus cycle with the interrupt level number output on pins A1–A3 of the address
bus. For a device that cannot supply an interrupt vector, the autovector signal (AVEC) can
be asserted, and the MC68030 uses an internally generated autovector, which is one of
vector numbers 25-31, that corresponds to the interrupt level number. If external logic
indicates a bus error during the interrupt acknowledge cycle, the interrupt is considered
spurious, and the processor generates the spurious interrupt vector number, 24. Refer to
7.4.1 Interrupt Acknowledge Bus Cycles for complete interrupt bus cycle information.
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MC68030 USER’S MANUAL
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