MC68030 Datasheet, PDF (441/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.2.6 Memory Management Unit
The MC68030 includes a memory management unit (MMU) that translates logical
addresses to physical addresses for external accesses when required. The MMU uses an
address translation cache (ATC) to store recently used translations. When the physical
address corresponding to a logical address resides in the ATC, the address translation time
is completely overlapped with on-chip cache accesses and has no effect on instruction
timing.
When the ATC does not contain the translation for a logical address, the processor performs
a table search operation to external memory. The amount of time required for a table search
depends on the structure of the address translation tree and whether a nonresident portion
of the translation tree is required.
The MMU supports demand-paged virtual memory. When a table search terminates with an
exception, indicating that the requested instruction or data is not resident, additional time to
bring the appropriate page into memory is required. The time required is dependent on the
handling routine for the exception.
11.3 INSTRUCTION EXECUTION TIMING CALCULATIONS
The instruction-cache-case timing, overlap, average no-cache-case timing, and actual
instruction-cache-case execution time calculations are discussed in the following
paragraphs.
11.3.1 Instruction-Cache Case
The instruction-cache-case (CC) time for an instruction is the total number of clock periods
required to execute the instruction, provided all the corresponding instruction prefetches are
resident in the on-chip instruction cache. All bus cycles are assumed to take two clock
periods. The instruction-cache-case time does not assume any overlap with other
instructions nor does it take into account hits in the on-chip data cache. The overall
instruction-cache-case time for some instructions is divided into the instruction-cache-case
time for the required effective address calculation (CCea) and the instruction-cache-case
time for the remainder of the operation (CCop). The instruction-cache-case times for all
instructions and addressing modes are listed in the tables of 11.6 Instruction Timing
Tables.
11-6
MC68030 USER’S MANUAL
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