MC68030 Datasheet, PDF (501/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
If the MC68851 is removed and replaced with a jumpered header, the following MC68851
signals may need special system-specific consideration: CLI, RMC, LBRO, LBG, LBGACK,
and LBGI. During translation table searches, the MC68851 asserts the cache load inhibit
(CLI) signal but not RMC; whereas, the MC68030 asserts RMC but not CIOUT. In simple
MC68020/MC68851 systems without logical bus arbitration or logical caches, the
MC68851's jumper can have the following signals connected together:
LAS ↔ PAS
LBRO ↔ PBR
LBGI ↔ PBG
LBGACK ↔ PBGACK
LA(8-31) ↔ PA(8-31)
CLI ↔ no connect or LAS
CLI has two connection options because some systems may use CLI to qualify the
occurrence of CPU space cycles since the MC68851's PAS does not assert.
12.1.3 Software Differences
The instruction cache control bits in the cache control register (CACR) of the MC68030 are
in the identical bit positions as the corresponding bits as the MC68020's CACR. However,
the MC68030 has additional control bits for burst enable and data cache control. Because
this adapter board does not support synchronous bus cycles (and thus burst mode),
enabling burst mode through the CACR does not affect system operation in any way. Refer
to Section 6 On-Chip Cache Memories for more information on the bit positions and
functions of the CACR bits.
When used in a system originally designed for an MC68020, a difference a programmer
must be aware of is that the MC68030 does not support the CALLM and RTM instructions
of the MC68020. If code is executed on the MC68030 using either the CALLM or RTM
instructions, an unimplemented instruction exception is taken. If no MMU software
development capability is desired and the cache behavior described under hardware
differences is understood, the user may ignore the MC68030 MMU.
When the adapter is used in a system originally designed for the MC68020/MC68851 pair,
the software differences described below also apply. The MC68030's MMU offers a subset
of the MC68851 features. The features not supported by the MC68030 MMU are listed be-
low:
• On-chip breakpoint registers
• Task aliasing
• Instructions: PBcc, PDBcc, PRESTORE, PSAVE, PScc, PTRAPcc, PVALID
12-4
MC68030 USER’S MANUAL
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