MC68030 Datasheet, PDF (536/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
(UNABLE TO LOCATE ART)
Figure 12-23. Trace Interface Circuit
Quantity
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2
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1
Table 12-5. List of Parts
Part
74F00
74F114
74F74
PAL16R6D
Part Description
Quad 2 Input NAND Gate
Dual JK Negative Edge-Triggered Flip-Flop
Dual D-Type Positive Edge-Triggered Flip-Flop
Programmable Logic Array, Ultra High Speed
The sample signal (SAMPLE) is an active-high signal which qualifies the next falling edge
of the CLK signal as the sampling point. Five types of conditions cause SAMPLE to assert:
1. An external bus cycle
2. An internal cache hit, including a hit in the cache holding register
3. An instruction boundary
4. Exception processing as marked by the EP signal discussed below
5. The processor halting
The remaining five output signals are used to qualify the information collected.
The processor halt (PHALT) signal indicates that the MC68030 has received a double bus
fault and needs a reset operation to continue processing. PHALT asserts after the assertion
of STATUS for greater than three clock cycles and generates a SAMPLE signal.
The FILL signal indicates a break in sequential instruction execution. FILL is a latched
version of the REFILL signal and remains asserted until a sample is collected as indicated
by the assertion of SAMPLE. The assertion of FILL does not generate a SAMPLE signal.
The exception pending (EP) signal indicates that the MC68030 is beginning exception
processing for either a reset, bus error, address error, spurious interrupt, autovectored
interrupt, F-line instruction, MMU address translation cache miss, trace exception, or
interrupt exception. The EP signal asserts after STATUS negates from a two- or three-clock
cycle assertion. The assertion of EP does generate a SAMPLE signal.
12-40
MC68030 USER’S MANUAL
MOTOROLA