MC68030 Datasheet, PDF (299/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
(UNABLE TO LOCATE ART)
Figure 9-7. Example Translation Tree Using Different Format Descriptors
All long-format descriptors and short-format invalid descriptors include one or two unused
fields. The operating system can use these fields for its own purposes. For example, the
operating system can encode these fields to specify the type of invalid descriptor.
Alternately, the external device address of a page that is not resident in main memory can
be stored in the unused field.
9.2 ADDRESS TRANSLATION
The function of the MMU is to translate logical addresses to physical addresses according
to control information stored by the system in the MMU registers and in translation table
trees resident in memory.
9.2.1 General Flow for Address Translation
A CPU space address (FC0-FC2=$7) is a special case that is immediately used as a
physical address without translation. For other accesses, the translation process proceeds
as follows:
1. Search the on-chip data and instruction caches for the required instruction word or op-
erand on read accesses.
2. Compare the logical address and function code to the transparent translation param-
eters in the transparent translation registers, and use the logical address as a physical
address for the memory access when one or both of the registers match.
3. Compare the logical address and function code to the tag portions of the entries in the
ATC and use the corresponding physical address for the memory access when a
match occurs.
4. When no on-chip cache hit occurs (on a read) and no TTx register matches or valid
ATC entry matches, initiate a table search operation to obtain the corresponding phys-
ical address from the corresponding translation tree, create a valid ATC entry for the
logical address, and repeat step 3.
Figure 9-8 is a general flowchart for address translation. The top branch of the flowchart
applies to CPU space accesses (FC0-FC2=$7). The next branch applies to read accesses
only. When either of the on-chip caches hits (contains the required data or instruction), no
memory access is necessary. The third branch applies to transparent translation. The
bottom three branches apply to ATC translation as follows. If the requested access misses
in the ATC, the memory cycle is aborted, and a table search operation proceeds. An ATC
entry is created after the table search, and the access is retried. If an access hits in the ATC
but a bus error was detected during the table search that created the ATC entry, the memory
access is aborted, and a bus error exception is taken.
MOTOROLA
MC68030 USER’S MANUAL
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