MC68030 Datasheet, PDF (499/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
12.1.1 Signal Routing
Figure 12-1 shows the complete schematic for routing the signals of the MC68030 to the
MC68020 header. All signals common to both processors are directly routed to the
corresponding signal of the other processor. The signals on the MC68030 that do not have
a compatible signal on the MC68020 are either pulled up or left unconnected:
Pulled Up
No Connect
TERM
STATUS
CBACK
REFILL
CIIN
CBREQ
MMUDIS
CIOUT
12.1.2 Hardware Differences
Before enabling the on-chip caches of the MC68030, an important system feature must be
checked. Because of the MC68030 cache organization and implementation, cachable read
bus cycles are expected to transfer the entire port width of data (as indicated by the DSACKx
encoding), regardless of how many bytes are actually requested by the SIZx pins. The
MC68020 did not have this requirement, and system memory banks or peripherals may or
may not supply the amount of data required by the MC68030. If the target system does not
supply the full port width with valid data for any cachable instruction or data access the user
should either designate that area of memory as noncachable (with the MMU) or not enable
the corresponding on-chip cache(s). In some systems, modifying the target system
hardware may also be an option; frequently, the byte select logic is generated by a single
PAL, which might easily be replaced or reprogrammed to select all bytes during read cycles
from multibyte ports.
The HALT input-only signal of the MC68030 is slightly different than the bidirectional HALT
signal of the MC68020. However, this should not cause any problems beyond eliminating
an indication to the external system (e.g., lighting an LED) that the processor has halted due
to a double bus fault.
When used in a system originally designed for both an MC68020 and an MC68851, the
MC68851 may be left in the system or removed (and replaced with a jumpered header).
However, if left in the system, the MC68851 is not accessible to the programmer with the
M68000 coprocessor interface. All MMU instructions access the MC68030's on-chip MMU.
This is true even if the MC68030's MMUDIS signal is asserted. The benefit in removing the
MC68851 is that the minimum asynchronous bus cycle time to the physical bus is reduced
from four clock cycles to three.
12-2
MC68030 USER’S MANUAL
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