MC68030 Datasheet, PDF (218/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
7.4.1.1 INTERRUPT ACKNOWLEDGE CYCLE — TERMINATED NORMALLY. When
the MC68030 processes an interrupt exception, it performs an interrupt acknowledge cycle
to obtain the number of the vector that contains the starting location of the interrupt service
routine.
Some interrupting devices have programmable vector registers that contain the interrupt
vectors for the routines they use. The following paragraphs describe the interrupt
acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply
a vector number and use the autovector cycle described in 7.4.1.2 Autovector Interrupt
Acknowledge Cycle.
The interrupt acknowledge cycle is a read cycle. It differs from the asynchronous read cycle
described in 7.3.1 Asynchronous Read Cycle or the synchronous read cycle described in
7.3.4 Synchronous Read Cycle in that it accesses the CPU address space. Specifically,
the differences are:
1. FC0–FC2 are set to seven (FC0/FC1/FC2=111) for CPU address space.
2. A1, A2, and A3 are set to the interrupt request level (the inverted values of IPL0, iPL1,
and IPL2, respectively).
3. The CPU space type field (A16-A19) is set to $F, the interrupt acknowledge code.
4. A20–A31, A4–A15, and A0 are set to one.
The responding device places the vector number on the data bus during the interrupt
acknowledge cycle. Beyond this, the cycle is terminated normally with either STERM or
DSACKx. Figure 7-43 is the flowchart of the interrupt acknowledge cycle.
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MC68030 USER’S MANUAL
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