MC68030 Datasheet, PDF (477/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.9 Immediate Arithmetical/Logical Instructions
The immediate arithmetical/logical operation timing table indicates the number of clock
periods needed for the processor to fetch the source immediate data value and to perform
the specified arithmetic/logical operation using the specified destination addressing mode.
Footnotes indicate when to account for the appropriate fetch effective or fetch immediate
effective address times. For instruction-cache case and for no-cache case, the total number
of clock cycles is outside the parentheses. The number of read, prefetch, and write cycles
is given inside the parentheses as (r/p/w). The read, prefetch, and write cycles are included
in the total clock cycle number.
All timing data assumes two-clock reads and writes.
MOVEQ
ADDQ
ADDQ
SUBQ
SUBQ
ADDI
ADDI
ANDI
ANDI
EORI
EORI
ORI
ORI
SUBI
SUBI
CMPI
CMPI
Instruction
#〈data〉,Dn
#〈data〉,Rn
#〈data〉,Mem
#〈data〉,Rn
#〈data〉,Mem
#〈data〉,Dn
#〈data〉,Mem
#〈data〉,Dn
#〈data〉,Mem
#〈data〉,Dn
#〈data〉,Mem
#〈data〉,Dn
#〈data〉,Mem
#〈data〉,Dn
#〈data〉,Mem
#〈data〉,Dn
#〈data〉,Mem
* Add Fetch Effective Address Time
**Add Fetch Immediate Effective Address Time
Head
2
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
Tail
I-Cache Case
No-Cache
Case
0
2(0/0/0)
2(0/1/0)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
0
2(0/0/0)
2(0/1/0)
11-42
MC68030 USER’S MANUAL
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