MC68030 Datasheet, PDF (275/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
Once the vector number is obtained, the processor saves the exception vector offset,
program counter value, and the internal copy of the status register on the active supervisor
stack. The saved value of the program counter is the logical address of the instruction that
would have been executed had the interrupt not occurred. If the interrupt was acknowledged
during the execution of a coprocessor instruction, further internal information is saved on the
stack so that the MC68030 can continue executing the coprocessor instruction when the
interrupt handler completes execution.
If the M bit of the status register is set, the processor clears the M bit and creates a
throwaway exception stack frame on top of the interrupt stack as part of interrupt exception
processing. This second frame contains the same program counter value and vector offset
as the frame created on top of the master stack, but has a format number of 1 instead of 0
or 9. The copy of the status register saved on the throwaway frame is exactly the same as
that placed on the master stack except that the S bit is set in the version placed on the
interrupt stack. (It may or may not be set in the copy saved on the master stack.) The
resulting status register (after exception processing) has the S bit set and the M bit cleared.
The processor loads the address in the exception vector into the program counter, and
normal instruction execution resumes after the required prefetches for the interrupt handler
routine.
Most M68000 Family peripherals use programmable interrupt vector numbers as part of the
interrupt request/acknowledge mechanism of the system. If this vector number is not
initialized after reset and the peripheral must acknowledge an interrupt request, the
peripheral usually returns the vector number for the uninitialized interrupt vector, 15.
8.1.10 MMU Configuration Exception
When the MC68030 executes a PMOVE instruction that attempts to move invalid data into
the TC, CRP, or SRP register of the MMU, the PMOVE instruction causes an MMU
configuration exception. The exception is a post-instruction exception; it is processed after
the instruction completes. The processor generates exception vector number 56 when an
MMU configuration exception occurs. Refer to Section 9 Memory Management Unit for a
description of the valid configurations for the MMU registers.
MOTOROLA
MC68030 USER’S MANUAL
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