MC68030 Datasheet, PDF (459/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6 INSTRUCTION TIMING TABLES
All the following assumptions apply to the times shown in the tables in this section:
• All memory accesses occur with two-clock bus cycles and no wait states.
• All operands in memory, including the system stack, are long-word aligned.
• A 32-bit bus is used for communications between the MC68030 and system memory.
• The data cache is not enabled.
• No exceptions occur (except as specified).
• Required address translations for all external bus cycles are resident in the address
translation cache.
Four values are listed for each instruction and effective address:
1. Head,
2. Tail,
3. Instruction-cache case (CC) when the instruction is in the cache but has no overlap,
and
4. Average no-cache case (NCC) when the instruction is not in the cache or the cache
is disabled and there is no instruction overlap.
The only instances for which the size of the operand has any effect are the instructions with
immediate operands and the ADDA and SUBA instructions. Unless specified otherwise,
immediate byte and word operands have identical execution times.
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MC68030 USER’S MANUAL
MOTOROLA